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HANBit
HSD32M64F8R
Synchronous DRAM Module 256Mbyte (32Mx64bit), SMM ,16Mx16, 4Banks, 8K Ref. 3.3V Part No. HSD32M64F8R
GENERAL DESCRIPTION
The HSD32M64F8R is a 32M x 64 bit Synchronous Dynamic RAM high-density memory module. The module consists of eight CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 120-pin glass-epoxy. Three 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD32M64F8R is a SMM(Stackable Memory Module type) .Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* Part Identification HSD32M64F8R-10L : 100MHz (CL=3) HSD32M64F8R-10 : 100MHz (CL=2) HSD32M64F8R-13 : 133MHz (CL=3) * Burst mode operation * Auto & self refresh capability (8K Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * The used device is 4M x 16bit x 4Banks SDRAM
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HANBit PIN ASSIGNMENT
BOTTOM P1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbo l Vcc DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 Vcc DQM4 DQM5 REGE CKE0 NC Vcc SDA SCL /CS1 /CS3 Vcc PIN 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbo l Vss DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Vss DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Vss DQM0 DQM1 /WE CLK0 CLK1 Vss /CAS /RAS /CS0 /CS2 Vss PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P2 Symbo l Vss DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Vss DQM2 DQM3 NC BA0 BA1 A10 A0 A1 A2 A3 Vss PIN 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol Vcc DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 Vcc DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Vcc DQM6 DQM7 A12 A11 A9 A8 A7 A6 A5 A4 Vcc PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symb ol Vcc DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 Vcc DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 Vcc DQM4 DQM5 REGE CKE0 NC Vcc SDA SCL /CS3 NC Vcc P3 PIN 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symb ol Vss DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Vss DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Vss DQM0 DQM1 /WE CLK0 CLK1 Vss /CAS /RAS /CS2 NC Vss
HSD32M64F8R
TOP P4 PI N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symb ol Vss DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Vss DQM2 DQM3 NC BA0 BA1 A10 A0 A1 A2 A3 Vss PIN 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbo l Vcc DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 Vcc DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 Vcc DQM6 DQM7 A12 A11 A9 A8 A7 A6 A5 A4 Vcc
* Pin Names A0~A12: Address input (Multiplexed) DQ0~DQ63: Data input/output CKE0: Clock enable input /RAS: Row address strobe /CAS: Coulmn address strobe DQM0~7: DQM REGE: Register enable SDA: Serial data I/O NC: No connection BA0~BA1: Select bank CLK0: Clock input /CS0, /CS2: Chip select input /WE: Write enable VSS: Ground Vcc: Power supply(3.3V) SCL: Serial clock DU: Don't use
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HANBit Functional Block Diagram
HSD32M64F8R
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HANBit PIN FUNCTION DESCRIPTION
Pin CLK /CE Name System clock Chip enable Input Function Active on the positive going edge to sample all inputs.
HSD32M64F8R
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command.
A0 ~ A12
Address
Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA8
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge.
/CAS
Column strobe
address
Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access.
/WE
Write
enable
Enables write operation and row precharge. Latches data in starting from /CAS, /WE active.
DQM0 ~ 7
Data mask
input/output
Makes data output Hi-Z, tsHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. The inputs are strobed in the latch/flip-flop on the riging edge of CLK. REGE is tied to VDD through 10K ohm register on PCB. So if REGE of module is floating, this module will be operated as registerd mode.
REGE
Register enable
DQ0 ~ 63 Vcc/Vss
Data input/output Power supply/ground
Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
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HANBit ABSOLUTE MAXIMUM RATINGS
HSD32M64F8R
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature
SYMBOL VIN ,OUT Vcc PD TSTG
RATING -1V to 4.6V -1V to 4.6V 8W -55oC to 150oC
Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4 UNIT V V V V V 1 2 IOH = -2mA IOL = 2mA 3 NOTE
Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(Vcc = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Input capacitance(A0~A11) Input capacitance(/RAS, /CAS,/WE) Input capacitance(CKE0) Input capacitance(CLK0) Input capacitance(/CE0,CE3) Input capacitance(DQM0~DQM7) Input capacitance(BA0~BA1) Data input/output capacitance (DQ0 ~ DQ63) SYMBOL CIN1 CIN2 CIN3 CIN4 CIN5 CIN3 CIN3 COUT MIN 2.5 2.5 2.5 2.5 2.5 2.5 2.5 4.0 MAX 5.0 5.0 5.0 4.0 5.0 5.0 5.0 6.5 UNITS pF pF pF pF pF pF pF pF
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HANBit DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T A = 0 to 70C) TEST PARAMETER SYMBOL CONDITION Burst length = 1 Operating current (One bank active) ICC1 tRC tRC(min) IO = 0mA Precharge standby current in power-down mode ICC2PS ICC2P CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= CKE VIH(min) ICC2N /CE VIH(min), tcc=10ns 160 8 8 960 880 -13 -10L VERSION
HSD32M64F8R
NOT UNIT -10 E
880
mA
1
mA
3
mA
3
Precharge standby current in non powerdown mode
Input signals are changed one time during 20ns CKE VIH(min) mA 3
ICC2NS
CLK VIL(max),
tcc=
56
Input signals are stable Active standby current in power-down mode ICC3P ICC3PS CKE VIL(max), tcc=10ns CKE&CLK VIL(max) tcc= CKEVIH(min), ICC3N /CEVIH(min), tcc=10ns 240 mA 3 40 mA 40 3
Active standby current in non power-down mode (One bank active)
Input signals are changed one time during 20ns CKEVIH(min)
ICC3NS
CLK VIL(max),
tcc=
160
Input signals are stable IO = 0 mA Operating current (Burst mode) ICC4 Page burst 1.2 4Banks Activated tCCD = 2CLKs Refresh current ICC5 tRC tRC(min) 1.76 1.68 12 1.68 A mA 2 3 1 1 A 1
CKE 0.2V Self refresh current ICC6 Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1PLL & 3 Drive Ics. 4. Unless otherwise noticed, input swing level is CMOS(V IH/VIL=VDDQ/VSSQ).
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HANBit AC OPERATING TEST CONDITIONS
(Vcc = 3.3V 0.3V, TA = 0 to 70C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
HSD32M64F8R
UNIT V V ns V
+3.3V
1200 DOUT 870 50pF*
Vtt=1.4V
50
vss
VOH (DC) = 2.4V, IOH = -2mA DOUT VOL (DC) = 0.4V, IOL = 2mA
Z0=50 50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay /RAS to /CAS delay Row precharge time Row active time SYMBOL -13 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 Number of valid output data CAS latency=2 1 65 15 20 20 45 -10L 20 20 20 50 100 70 2 2 CLK + 20 ns 1 1 1 2 ea 4 80 -10 20 24 24 50 ns ns ns ns ns ns CLK CLK CLK CLK 1 2,5 5 2 2 3 1 1 1 1 UNIT NOTE
Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay
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HANBit
HSD32M64F8R
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .5. For -1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.)
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) -13 PARAMETER CAS 7.5 CLK cycle time latency=3 tCC CAS latency=2 CLK to valid output delay Output latency=3 data CAS hold time latency=2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS CLK to latency=3 output CAS in Hi-Z latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered i.e., [(tr + tf)/2-1]ns should be added to the parameter. 7 7 ns tSHZ 5.4 6 7 ns tCH tCL tSS tSH tSLZ 2.5 2.5 1.5 0.8 1 3 3 2 1 1 3.5 3.5 2.5 1.5 1 ns ns ns ns ns 3 3 3 3 2 3 3 tOH ns 2 CAS 5.4 latency=3 tSAC CAS latency=2 CAS 2.7 3 3 7 7 ns 1,2 6 7 12 13 1000 1000 1000 ns 1 10 10 SYMBOL Min Max Min Max Min Max -10L -10 UNIT NOTE
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HANBit
SIMPLIFIED TRUTH TABLE /R A S L L H X L /C A S L L H X H D Q M X X X X V
HSD32M64F8R
COMMAND Register Mode register set Auto refresh Refresh Self refres h Auto disable Auto eable Auto disable Auto enable precharge precharge precharge Entry Exit
CKE n-1 H H L H
CKE n X H L H X
/C E L L L H L
/W E L H H X H
BA 0,1
A10/ AP OP code X X
A11 A9~A0
NOTE 1,2 3 3 3 3
Bank active & row addr. Read & column address Write & column address Burst Stop Precharg e Bank selection All banks Entry Exit Entry Exit precharge
Row address L Column Address H (A0 ~ A9) Column Address H (A0 ~ A9) X 4,5 6 X 4,5 4 4
H
X
L
H
L
H
X
V
H H X L H L L H H H L H L H H X H L X X L H L H L L H L X H L H L H L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X V X X V
L
L H X
Clock suspend or active power down
Precharge down mode DQM
power
X X V X X X 7
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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HANBit TIMING DIAGRAMS
HSD32M64F8R
td, tr = Delay of register (74LVC162835) Notes : 1. In case of module timing, command cycles 1CLK with respect to external input timing at the address and input signal because of the buffering in register (74LVC162835). Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as compared to Unbuffered MODULE. 2. DIN is to be issued 1 clock after write command in external timing because D IN is issued directly to module.
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit
HSD32M64F8R
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HANBit PACKAGING INFORMATION
Unit : inch [mm] TOLERANCE : 0.008 [ 0.20 ] Front - Side
HSD32M64F8R
Rear-Side
ORDERING INFORMATION
Part Number
Density
Org.
Package 120PIN STACKABLE 120PIN STACKABLE 120PIN STACKABLE
Ref.
Vcc
MODE
MAX.frq 100Mhz CL=2 100Mhz CL=3 133Mhz CL=3
HSD32M64F8R-10 HSD32M64F8R-10L HSD32M64F8R-13
256MByte 256MByte 256MByte
32M x 64 32M x 64 32M x 64
8K 8K 8K
3.3V 3.3V 3.3V
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